The Performance And Stability Of Hydrogenated Amorphous Silicon Thin Film Transistors PDF Download

The integration of memory circuits in thin-film transistors (TFTs) is essential to extend the functionalities of large-area applications such as flat-panel displays, imagers etc. Intensive research is being conducted with the goal of producing high-performance memory devices for active-matrix backplane electronics. For example, a memory in a pixel circuit has the potential to reduce the refresh rate for display applications. This eventually leads to reduced power consumption which is vital for producing low-power displays. In addition, memory in pixel circuits can improve the fill factor of the display by its ability to hold the data without the need for a storage capacitor. Prior work has reported various TFT structures justifying the performance of the devices especially on their behavior under floating conditions. This work investigates the effect of continuous read cycles on the stability of low-temperature hydrogenated amorphous silicon (a-Si:H) memory TFTs prepared using the industrial standard back-channel etched (BCE) TFT process, as the topic yet to be explored systematically. An engineered charge-trapping interface between the gate dielectric and the channel layer is fabricated to realize non-volatile memory. The performance of the devices was initially measured by comparing the transfer characteristics of the memory TFTs with conventional a-Si:H TFTs. The stability of the memory devices was measured under different stress conditions by varying the gate voltage and stress time. An emphasis was placed on the stability of the memory devices under floating and persistent read cycles as followed in display applications. The drain current was measured over various intervals of time for ~60 days to track the degradation of the devices. The reliability of the memory devices was also measured. From the analysis of the results, the charge-trapping memory TFTs demonstrated good stability, large memory window, and better endurance. The charge retention of the devices under floating conditions was extrapolated and it showed a lifetime of ~10 years. However, the charge retention of the memory TFTs exhibited a 50% decrease in lifetime under realistic persistent read bias conditions (~5 years). This is possibly due to the instability of a-Si:H devices. This lifetime is subjected to change under different read voltage. Hence, the lifetime under continuous read cycles is extremely important to provide boundaries for expected memory lifetimes under normal display operating conditions.