Simulation Of Transport In Nanodevices PDF Download

The semiconductor industry, in its continued effort to scale down nanoscale components further, needs to predict the physical properties of future components. As the size of such devices shrinks down, the currently prevalent semi-classical models start to fall apart, as quantum effects that are usually invisible in larger silicon devices gain in relevance in smaller and/or III-V based semiconductor devices. Therefore, modeling and simulation tools should describe adequately the favorite technological options that are currently under investigation. Consequently, full quantum simulations are necessary to the development of modern field effect transistors.The purpose of this PhD thesis is to develop the tools suitable for those simulations and use them to look into some of the most relevant design options for transistor technology.Hence, we used the Non Equilibrium Green's Functions formalism to simulate charge carriers transport and investigate field effect transistors.The semiconductor band structures were calculated within a continuous kp formalism, but we also developed an atomistic effective pseudopotential method to perform full-band simulations with a variety of ingredients like arbitrary crystal orientation, surface roughness, arbitrary alloy composition in the transistor channel, and so on. This pseudopotential method provides accurate results for a wider array of configurations with a smaller parametrization effort than the k.p formalism.We used these simulation tools to evaluate the transport properties of silicon and InAs based FinFETs, focusing on the supply-voltage scalability of III-V based devices compared to silicon counterparts. In particular, the feasibility of obtaining large on-current values in III-V devices is discussed.Then, we applied that formalism to III-V based gate all-around (GAA) nanowire tunnel-FETs (TFETs). Tunnel-FETs are a promising architecture for future transistors, facing optimization and performance challenges. We aimed at benchmarking the effect of technological boosters on the performances of TFETs, namely the use of strain engineering and of III-V heterojunctions. We've shown that these boosters allow TFETs to theoretically outperform standard MOSFET technology, but that strain engineering induces undesirable drawbacks.In order to design high performance TFETs without the use of strain, we finally introduced novel design options by exploiting a molar fraction grading of a ternary alloy or alternatively a quantum well in the source region. These device configurations dramatically change the density of state of the TFET at the source/channel junction and are therefore able to improve the electrical performance of TFETs with respect to conventional MOSFETs.