Modeling Of Chemical Mechanical Polishing At Multiple Scales PDF Download

Chemical Mechanical Polishing (CMP) has grown rapidly during the past decade as part of mainstream processing method in submicron integrated circuit manufacturing because of its global or near-global planarization ability. However, CMP process is influenced by many factors and is poorly understood. It makes process control and optimization very difficult. This study focuses on the modeling and simulation to facilitate better understanding and better control of the CMP process. The thesis outlines the modeling of CMP process in three scales: particle scale for material removal mechanism, wafer scale for within wafer nonuniformity issues and feature scale for dishing and erosion in metal CMP. At the particle scale, material removal mechanism is assumed to be due to local plastic deformation of wafer surface material. A mechanistic material removal model is derived that delineates the influence of abrasive (shape, size and concentration), pad (rigidity) and process parameters (pressure and relative velocity) on the material removal rate (MRR). Wafer scale model is based on the solution of indentation of elastic half space by a rigid frictionless polynomial punch. The load-displacement relationship is also derived and the conditions for unbonded or bonded contact are obtained from the boundary condition at punch edge. The corresponding viscoelastic solution is obtained through Laplace transform and elastic-viscoelastic analogy. The elastic solution is used to explain the edge effect. Viscoelastic solution is used to explain MRR decay for unconditioned pad. The relationships among wafer-pad interface pressure, wafer shape and wafer loading condition are also investigated. Feature scale model is based on Preston's relationship for material removal and constant downforce. It shows dishing is governed by polishing conditions (overpolishing, pressure, velocity), slurry (selectivity), pad characteristics (pad stiffness and bending ability), as well as wafer surface feature topography (pattern density, linewidth and pitch). This model is also valid for step height reduction when the same surface material is polished. Due to process complexity and coupling of various parameters, more fundamental research needs to be carried out and carefully designed experiments need to be done to verify the models. Recommendations for future research work is presented at the end.