Low Power Smart Cmos Image Sensors With Embedded Mixed Signal Image Processing PDF Download

"Ever since the invention of Charged Coupled Devices (CCD) and CMOS image sensors, there have been tremendous development efforts towards the creation of digital cameras, which rapidly replaced traditional analog and film cameras. Despite their leading role in the market today, most digital cameras still exhibit worse image quality than film cameras. Many efforts have been made to improve the performance of digital images, such as increased dynamic range and reduced readout noise. As one of the fastest growing industries worldwide, CMOS imaging ranges from high quality digital still cameras to low quality consumer end products. Compared to CCD image sensors, CMOS image sensors allow low power, low cost and on-chip signal processing, which allow them to become more and more prominent. However, the demand for low noise, high readout speed and high dynamic range is still a big concern for CMOS imagers. The goal of this work is to improve the readout time while decreasing the readout noise by employing a modification to the standard Active Pixel Sensor (APS) design to retain high fill factor. The first part of this work focused on a new design named Current Sensing Active Pixel (CSAP) sensor. The design was an analog CMOS image sensor readout architecture implemented in a standard 0.35 [microns] CMOS process, operating from a 3.3 V power supply with faster readout settling times than the standard APS design. The standard APS source follower configuration is used in the pixel part of the CSAP design to obtain a high fill factor. The CSAP design also employed an out-of-pixel readout amplifier in the negative feedback topology with respect to the pixel unit to increase the pixel's current driving capabilities and thereby reduce the settling time at the output. As a result of improved settling time, the 1/f noise contributed by the inpixel source follower transistor may be significantly reduced by the correlated double sampling (CDS) operation commonly used in analog image sensor readout methods. The fabricated CSAP chip prototype was successfully tested and some of the performance improvements were also demonstrated. The other part of this thesis was a new design named Reconfigurable Active Pixel Sensor (RAPS). It was also an analog CMOS image sensor readout architecture implemented in a standard 0.35 [microns] CMOS process operating from a 3.3 V power supply. This design eliminated the need for the external correlated double sampling (CDS) circuit that is used in traditional APS designs. It employed a reconfigurable differential-input readout amplifier that may be used in both the reset and the readout phases of the image sensor operation. As a result, the DC offset was removed, the flicker noise was differentiated, and the reset noise was greatly reduced by employing the amplifier in an active reset configuration. Gain related fixed pattern noise (FPN) was also reduced by the higher open-loop gain of the differential amplifier. This design retained a high fill factor since the pixel unit utilized the same number and size of transistors as the standard APS design"--Leaves iv-v.