Hot Carrier Reliability Assessment In Cmos Digital Integrated Circuits PDF Download

The goals of the research work presented in this thesis are to model submicron pMOS transistor hot-carrier degradation and to develop a fast reliability simulation tool for hot-carrier reliability analysis of CMOS VLSI circuits. This simulator should be able to handle very large submicrometer circuits accurately and efficiently. As device sizes shrink into the submicron region, pMOS transistor hot-carrier degradation becomes increasingly more important. There has not, however, been a widely accepted model for pMOS transistor hot-carrier degradation unlike that for nMOS transistors. Existing reliability simulations tools are primarily based on transistor level simulation and, therefore, can not handle large circuits efficiently. Using the fast-timing-based reliability simulator, ILLIADS-R, and the empirical model developed based on our experimental results, hot-carrier reliability can be well predicted. ILLIADS-R also serves as an integral part of the hierarchical design-for-reliability system. A new hot-carrier degradation model is developed for submicron pMOS transistors. Using this model, the pMOS transistor hot-carrier degradation can be predicted based on the total injected charge into the gate oxide region and the initial gate current under normal operating condition. This model is integrated into the fast-timing-based reliability simulation tool, ILLIADS-R. The simulation results demonstrate that ILLIADS-R outperforms the existing reliability simulator BERT in terms of simulation speed with a comparable accuracy. Also studied are the pMOS transistor subthreshold leakage characteristics as a function of hot-carrier stress conditions. It is shown that subthreshold leakage current is a future limit to the pMOS device lifetime.