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Error Control for Network-on-Chip Links

Error Control for Network-on-Chip Links
Author: Bo Fu
Publisher: Springer Science & Business Media
Total Pages: 159
Release: 2011-10-09
Genre: Technology & Engineering
ISBN: 1441993134

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This book provides readers with a comprehensive review of the state of the art in error control for Network on Chip (NOC) links. Coverage includes detailed description of key issues in NOC error control faced by circuit and system designers, as well as practical error control techniques to minimize the impact of these errors on system performance.


Transient and Permanent Error Control for Networks-on-Chip

Transient and Permanent Error Control for Networks-on-Chip
Author: Qiaoyan Yu
Publisher: Springer Science & Business Media
Total Pages: 166
Release: 2011-11-18
Genre: Technology & Engineering
ISBN: 1461409624

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This book addresses reliability and energy efficiency of on-chip networks using cooperative error control. It describes an efficient way to construct an adaptive error control codec capable of tracking noise conditions and adjusting the error correction strength at runtime. Methods are also presented to tackle joint transient and permanent error correction, exploiting the redundant resources already available on-chip. A parallel and flexible network simulator is also introduced, which facilitates examining the impact of various error control methods on network-on-chip performance.


Network-on-Chip

Network-on-Chip
Author: Santanu Kundu
Publisher: CRC Press
Total Pages: 392
Release: 2018-09-03
Genre: Technology & Engineering
ISBN: 1351831968

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Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems.


Transient and Permanent Error Control for Networks-on-Chip

Transient and Permanent Error Control for Networks-on-Chip
Author: Qiaoyan Yu
Publisher: Springer
Total Pages: 160
Release: 2014-01-25
Genre: Technology & Engineering
ISBN: 9781489991935

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This book addresses reliability and energy efficiency of on-chip networks using cooperative error control. It describes an efficient way to construct an adaptive error control codec capable of tracking noise conditions and adjusting the error correction strength at runtime. Methods are also presented to tackle joint transient and permanent error correction, exploiting the redundant resources already available on-chip. A parallel and flexible network simulator is also introduced, which facilitates examining the impact of various error control methods on network-on-chip performance.


Transient and Permanent Error Management for Networks-on-chip

Transient and Permanent Error Management for Networks-on-chip
Author: Qiaoyan Yu
Publisher:
Total Pages: 502
Release: 2011
Genre:
ISBN:

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"Reliability has become one of the most important metrics for on-chip communications infrastructures in nanoscale technologies. Reduced supply voltages and high clock frequency exacerbate the impact of noise sources such as particle strikes and crosstalk, which can cause transient errors in transmitted data. Manufacturing defects and aging issues can cause permanent errors in the communication links. The modularity of the Networks-on-Chip (NoCs) approach facilitates the exploration of error control techniques for on-chip interconnects and many-cores systems. Unfortunately, error control is not free. Worst-case error management methods are simple but waste energy and bandwidth in favorable noise conditions. Consequently, cost-effective techniques for improving link error resilience are needed. In this work, we propose configurable error control methods to tackle variable transient errors and exploit existing transient error control redundancy for permanent error management, achieving high reliability and low average energy consumption with minor area overhead. To adapt to the variable transient error rates, a configurable error control coding (ECC) scheme is proposed for datalink-layer transient error management. The proposed method can adjust both error detection and error correction capability at runtime by varying the number of redundant wires for parity check bits. The obtained error resilience makes the proposed method suitable for a range of link error rates. Configuring the number of redundant wires to match the noise conditions reduces the average energy consumption in the ECC codec and interconnect link. A hardware efficient implementation for the configurable ECC is presented, as well. We integrate the error control techniques in the datalink and physical layers to co-manage transient and permanent errors. Infrequently used redundant wires for the configurable ECC are utilized as spare wires to replace permanently unusable links. To maintain the transient and permanent error co-management capability as noise conditions change, we propose a packet re-organization algorithm combined with shortening error control coding method. This method reduces the need for energy consuming fault-tolerant routing, minimizing latency and energy overhead induced by error control. This co-management method is suitable for NoCs operating in variable noise conditions with a small number of permanently unusable wires. To further improve energy efficiency, the adaptation on ECC is extended to the network layer. We employ end-to-end error control in the network layer in low noise conditions and enhance the error control capability in high noise conditions by adding hop-to-hop error control in the datalink layer. A protocol that boosts or reduces error control strength is presented to support runtime seamless ECC mode switching. Simply combining end-to-end error control with hop-to-hop error control significantly increases energy consumption. To address this issue, we apply the concept of product codes to the dual-layer error control; the hop-to-hop error control is designed to be compatible with one dimension of the product code. Consequently, the dual-layer cooperative error control can switch error control modes without interrupting normal NoC operation, achieving high reliability and energy efficiency in a wide range of link error rates. To evaluate performance and energy consumption of different error control methods on a large size NoC, we propose a flexible parallel NoC simulator. Plug-and-play error control coding (ECC) insertion and some typical error control codecs have been implemented in the simulator. The flexible fault injection environment provided by our simulator assists error control exploration for specific purposes. In addition, we use C and message passing interface (MPI) languages to schedule parallel simulation on a multiprocessor server, addressing the prohibitive simulation time and system resource challenges caused by the large number of communicating nodes and extensive number of simulation variables"--Leaves iv-vi.


Network-on-Chip

Network-on-Chip
Author: Santanu Kundu
Publisher: CRC Press
Total Pages: 388
Release: 2018-09-03
Genre: Technology & Engineering
ISBN: 1466565276

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Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems.


Asynchronous On-Chip Networks and Fault-Tolerant Techniques

Asynchronous On-Chip Networks and Fault-Tolerant Techniques
Author: Wei Song
Publisher: CRC Press
Total Pages: 381
Release: 2022-05-10
Genre: Computers
ISBN: 1000578828

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Asynchronous On-Chip Networks and Fault-Tolerant Techniques is the first comprehensive study of fault-tolerance and fault-caused deadlock effects in asynchronous on-chip networks, aiming to overcome these drawbacks and ensure greater reliability of applications. As a promising alternative to the widely used synchronous on-chip networks for multicore processors, asynchronous on-chip networks can be vulnerable to faults even if they can deliver the same performance with much lower energy and area compared with their synchronous counterparts – faults can not only corrupt data transmission but also cause a unique type of deadlock. By adopting a new redundant code along with a dynamic fault detection and recovery scheme, the authors demonstrate that asynchronous on-chip networks can be efficiently hardened to tolerate both transient and permanent faults and overcome fault-caused deadlocks. This book will serve as an essential guide for researchers and students studying interconnection networks, fault-tolerant computing, asynchronous system design, circuit design and on-chip networking, as well as for professionals interested in designing fault-tolerant and high-throughput asynchronous circuits.


Dependable Multicore Architectures at Nanoscale

Dependable Multicore Architectures at Nanoscale
Author: Marco Ottavi
Publisher: Springer
Total Pages: 294
Release: 2017-08-28
Genre: Technology & Engineering
ISBN: 3319544225

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This book provides comprehensive coverage of the dependability challenges in today's advanced computing systems. It is an in-depth discussion of all the technological and design-level techniques that may be used to overcome these issues and analyzes various dependability-assessment methods. The impact of individual application scenarios on the definition of challenges and solutions is considered so that the designer can clearly assess the problems and adjust the solution based on the specifications in question. The book is composed of three sections, beginning with an introduction to current dependability challenges arising in complex computing systems implemented with nanoscale technologies, and of the effect of the application scenario. The second section details all the fault-tolerance techniques that are applicable in the manufacture of reliable advanced computing devices. Different levels, from technology-level fault avoidance to the use of error correcting codes and system-level checkpointing are introduced and explained as applicable to the different application scenario requirements. Finally the third section proposes a roadmap of future trends in and perspectives on the dependability and manufacturability of advanced computing systems from the special point of view of industrial stakeholders. Dependable Multicore Architectures at Nanoscale showcases the original ideas and concepts introduced into the field of nanoscale manufacturing and systems reliability over nearly four years of work within COST Action IC1103 MEDIAN, a think-tank with participants from 27 countries. Academic researchers and graduate students working in multi-core computer systems and their manufacture will find this book of interest as will industrial design and manufacturing engineers working in VLSI companies.


Network-on-Chip Security and Privacy

Network-on-Chip Security and Privacy
Author: Prabhat Mishra
Publisher: Springer Nature
Total Pages: 496
Release: 2021-06-04
Genre: Technology & Engineering
ISBN: 3030691314

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This book provides comprehensive coverage of Network-on-Chip (NoC) security vulnerabilities and state-of-the-art countermeasures, with contributions from System-on-Chip (SoC) designers, academic researchers and hardware security experts. Readers will gain a clear understanding of the existing security solutions for on-chip communication architectures and how they can be utilized effectively to design secure and trustworthy systems.