Design And Test Strategies For 2d 3d Integration For Noc Based Multicore Architectures PDF Download

Manycore architecture exploits tremendous computation capability for highly parallelized workloads and big data analysis. Manycore chip uses network-in-chip (NoC) to transfer message between core-to-core and memory. Three-dimensional (3D) NoC provides a scalable, high-performance and energy-efficient communication backbone. By taking advantage of the shorter distance in z-dimension, 3D NoC enables lower latency and energy consumption compared to the 2D counterpart. Through-silicon-vias (TSVs) based 3D NoC suffers from several fabrication and reliability imperfections. Recently, monolithic 3D (M3D) architecture has been proposed as an alternative to TSV-based design. M3D technology enables high density integration by sequentially stacking tiers on top of each other using minuscule monolithic inter-tier vias (MIVs). In M3D fabrication, the active layers are fabricated on the same die and high temperature annealing can damage the chip. This has necessitated low temperature annealing techniques for M3D fabrication, leading to inferior performance of transistors in the top tier and slower interconnects in bottom tier. To this end, we developed a process-variation aware monolithic 3D NoC design technique to place the NoC components optimally and minimize the effect of process related degradation. Manycore chip also suffers from thermal hotspots resulting from power-hungry processors. Voltage frequency island (VFI)-based power management is a popular strategy to enhance the energy efficiency of a manycore chip without incurring noticeable performance degradation. The heart of a VFI-based system is changing the voltage/frequency (V/F) pairs of each island to match the requirements of a dynamically varying workload. However, negative bias temperature instability (NBTI) increases the threshold voltage of PMOS transistors, leading to timing failures for fixed V/F pairs. Hence, we propose an online NBTI-aware VFI design to improve the chip lifetime and energy efficiency while dynamically tuning V/F pairs. Modern mobile chip is shifting from traditional homogenous structure to heterogenous one to support diverse workloads. In mobile chips, the resource management technique needs to fulfil two contradictory objectives: energy efficiency with application wise performance requirements. Moreover, smartphones also run numerous unseen applications throughout the lifetime. Hence, we propose a machine learning based resource management strategy to adapt in presence of multiple new applications.