Design And Implementation Of Frequency Synthesizers For 3 10 Ghz Mulitband Ofdm Uwb Communication PDF Download

Abstract: In this thesis the design of low phase noise frequency synthesizers for emerging wireless applications is investigated. The future wireless applications employ Orthogonal Frequency Division Multiplexing (OFDM) in order to combat the harsh mobile environment effects on the signal, such as Doppler effect or Multi-path fading. However, OFDM imposes the stringent integrated phase noise requirement to maintain the orthogonality of the subcarriers. The emerging applications also require broadband functionality to cover the multiple bands specified by different application using a single frequency synthesizer. Particularly, this thesis focuses on the design of SD fractional-N frequency synthesizers for OFDM based applications. SD fractional-N PLLs have proven to be a very good candidate for the emerging OFDM-based radios which require employment of fast switching low phase noise frequency synthesizers. The issue of spectral Purity in SD PLLs is discussed, and the issue of phase noise and fractional spurs is investigated. Considering the loop dynamics, the optimal design for low phase noise is described. The problem of noise folding and its impact on spur cancellation is studied. A type-I second order PLL is designed which inherently eliminates the sources of nonlinearity in the signal path. The LO generation scheme is proposed to cover the three bands of WiMAX application centered at 2.5, 3.5 and 5.5 GHz by utilizing a broadband PLL. The design employs a uniformly sampled two state PFD and a discrete on-chip filter. A cancellation DAC in embedded in the PFD which is used to cancel out the phase induced by quantization error. The design enhances the noise folding and spur performance and satisfies the stringent integrated phase noise requirement of the application. As a critical part of the top-down design, a system study for a dual-band DVB-H tuner is presented. The tuner's various requirements in terms of linearity, gain and noise are derived. The required of phase noise of the PLL is calculated on the basis of the blocker profile of the tuner. The direct conversion architecture is adopted for the design and the specification of various blocks in the radio is derived in order to satisfy the required performance. The LO generation scheme for dual band local oscillator is proposed. Finally, the design of key circuits in the PLL loop is presented. The wideband VCO for triple WiMAX application is utilizing an amplitude regulation scheme to minimize supply pushing and improve the spectral purity. The high-speed multi-modulus divider design is presented. The design of high-speed broadband divide-by-32/33 dual modulus prescaler is described.