Concepts Design Of Integrated Circuits For Bidirectional Neural Interfaces PDF Download

Realizations of small-form factor, ultra-low power bidirectional brain-computer interfaces (BBCIs) will enable treatment of chronic neurophysiological disorders and allow new modes to investigate brain function. Neural stimulators have been shown to effectively alleviate the symptoms of various neurological disorders, and development of closed-loop bidirectional neural interfaces will increase therapy effectiveness by adapting to real-time measurements. This dissertation studies implementation of neural interface functionality in a single chip consuming minimal power and silicon area with two novel techniques: a. Time-multiplexed, mixed-signal artifact cancellation for simultaneous stimulation and sensing; b. Compact integrated stimulators with on-chip resonant charge pumps. The following paragraphs enumerate the two proposed techniques and their associated challenges and advantages. First, integrated artifact cancellation allows uninterrupted recording of neural signals during stimulation pulses in adjacent tissue. Existing low-frequency signals can be preserved, and an artifact-immune recording system can quantify the body0́9s immediate response to stimulation. Cancelling artifacts is complicated by the magnitude difference between stimulation pulses and neural signals of interest. Stimulation artifacts are several orders of magnitude larger than the upper dynamic range of typical recording systems, so a canceller requires specialized front-end electronics. Stimulus artifact cancellation has been demonstrated with digital adaptive filters interfacing with a switched-capacitor analog recording front-end. On cue from the stimulator, the adaptive filter learns the artifact shape based on recording output and subtracts the full stimulus artifact waveform from the recording input. The technique was first prototyped with an FPGA-based adaptive filter interfacing with standalone recording and stimulation chips. Later, the algorithm was optimized for power-efficient operation over multiple stimulation and recording channels. It was then integrated into a multi-channel bidirectional interface capable of cancelling artifacts from four independent stimulators on four recording channels. The power-efficient canceller was fabricated in the 65nm TSMC low-power CMOS process, allowing use of low-voltage supplies for the calculation back-end. This enabled 60dB of artifact suppression with a full-scale limit of ±125mV while only consuming 49nW per channel. Second, effectively stimulating neural tissue through low form-factor electrodes requires high voltages to drive current through large electrode impedances. These stimulation voltages often exceed the maximum voltage ratings of the high-density CMOS technologies desired for compact neural interfaces. Stacked charge pumps are often used to generate large voltages with multiple low-voltage stages, protecting CMOS electronics. Standard charge pump implementations pump charge with large capacitors at low frequencies to maintain power efficiency. In these cases, charge pump capacitor area dominates the system size. The proposed stimulator uses resonant clocking techniques to maintain efficiency with small charge pump capacitors clocked at high frequencies. An integrated inductor creates a resonant tank with the charge pump capacitors, compensating for switching losses in the circuit. This technique was demonstrated in a multi-channel BBCI chip. Four independent differential stimulators were integrated with a 64-channel recording system and the previously mentioned artifact cancellation back-end in a 4mm2 65nm CMOS chip. The stimulators source up to 2mA of stimulation current with a range of ±11V. The internal charge pumps supply power with a DC-DC efficiency of 38%, as compared to the possible 6% of a theoretical non-resonant topology of equal size.