A Preliminary Architecture For A Basic Data Flow Processor PDF Download

Computer has evolved rapidly during the past several decades in terms of its implementation technology; it's architecture, however, has not changed dramatically since the von Neumann computer(control flow) model emerged in the 1940s. One main reason is that the performance for this kind of computers was able to satisfy the requirement of most users. Another reason maybe that the engineers who designed them are more familiar with this model. However, recent solutions to the problem of parallelizing sequential nature instructions on a von Neumann machine complicate both the compiler and the controller design. Therefore, another computer model, namely the data flow model, has regained attention since this model of computation exposes parallelism inherent in the program naturally. In terms of implementation methodology, we currently use synchronous sequential logic, which is clock controlled for synchronization within circuits. This design philosophy becomes hard to follow due to the occurrence of clock skew as the clock frequency goes higher and higher. One way to eliminate these clock related problems is to use the self-timed(asynchronous) implementation methodology. It features advantages such as free of clock-skew, low power consumption, composibility and so forth. Since data flow(data driven) computation model provides the execution of instructions asynchronously, it is natural to implement a data flow processor using self-timed circuits. In this thesis, micro pipelines, one of the self-timed implementation methodology, is used to implement a preliminary version of general purpose static data flow processor. Some interesting observations will be addressed in this thesis. An example program of general difference recursive equation is given to test the correctness and performance of this processor. We hope to gain more insight on how to design and implement self-timed systems in the future.